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dsPIC30F
9.12
I/O Pins
I/O port pins have latch bits (Port Latch register). This
Some pins for the I/O pin functions are multiplexed with
an alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
All I/O port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register determines whether the pin is an input or an
output. The Port Data Latch register provides latched
output data for the I/O pins. The Port register provides
visibility of the logic state of the I/O pins. Reading the
Port register provides the I/O pin logic state, while
writes to the Port register write the data to the port Data
Latch register.
? 2005 Microchip Technology Inc.
register, when read, yields the contents of the I/O latch,
and when written, modifies the contents of the I/O latch,
thus modifying the value driven out on a pin if the
corresponding Data Direction register bit is configured
for output. This can be used in read-modify-write
instructions that allow the user to modify the contents
of the latch register, regardless of the status of the
corresponding pins.
The I/O pins have the following features:
? Schmitt Trigger input
? CMOS output drivers
? Weak internal pull-up
The Input Change Notification module gives dsPIC30F
devices the ability to generate interrupt requests to the
processor in response to a change of state on selected
input pins. This module is capable of detecting input
changes of state even in Sleep mode, when the clocks
are disabled. There are up to 24 external signals (CN0
through CN23) that can be selected (enabled) for
generating an interrupt request on a change of state.
Each of the CN pins also has an optional weak pull-up
feature.
DS70043F-page 33
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